11:44 Mar 31, 2004 |
English language (monolingual) [PRO] Tech/Engineering - Electronics / Elect Eng | |||||||
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| Selected response from: Tony M France Local time: 08:43 | ||||||
Grading comment
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SUMMARY OF ALL EXPLANATIONS PROVIDED | ||||
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5 +1 | Yes, Elena... |
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4 +1 | synchronization error |
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5 | scarto |
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3 -1 | error |
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error Explanation: A term used in RF systems to describe the situation when two devices having different impedances are connected to each other. Mismatches cause excess signal losses and other problems. www.audio-technica.com/glossary/ |
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Yes, Elena... Explanation: Here, 'mismatch' is being used to refer to a difference in the arrival time of the two signals at the defined point in the circuit. Indeed, a timing 'error'; the arrival times of the two signals are 'not matched' -------------------------------------------------- Note added at 9 hrs 24 mins (2004-03-31 21:09:08 GMT) -------------------------------------------------- In response to mk_lab\'s peer response to my comment. Sorry, I\'m afraid I can\'t even understand your response! I don\'t follow the distinction you seem to be trying to make between \'mismatch duration\' and \'value of mismatch\'? In any event, the context given makes it pretty clear to me that 3 s IS indeed the duration: \"...a mismatch of more than 3 seconds...\" What else could it mean? I\'m sure all this means is that the two signals A and B (whatever those may be) must arrive within 3 seconds of each other, or else an error is generated. I believe it\'s as simple as that, and we don\'t need to go looking any further into more complex questions of clocking, data skew, etc.... |
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synchronization error Explanation: . -------------------------------------------------- Note added at 13 mins (2004-03-31 11:57:42 GMT) -------------------------------------------------- Synchronization error from mismatch in feedback time delay . ... www.phy.duke.edu/~illing/papers/slas.pdf -------------------------------------------------- Note added at 5 hrs 25 mins (2004-03-31 17:10:09 GMT) -------------------------------------------------- mismatch here is equal to \"delay\" of clock signals in one of input channels (A or B) -------------------------------------------------- Note added at 20 hrs 7 mins (2004-04-01 07:51:59 GMT) -------------------------------------------------- As responce to Dusty\'s comment: \"I\'m sure all this means is that the two signals A and B (whatever those may be) must arrive within 3 seconds of each other, or else an error is generated. I believe it\'s as simple as that, and we don\'t need to go looking any further into more complex questions of clocking, data skew, etc....\" It\'s difficult to be sure wothout detailed description of the circuit, but I guess that signal mismatch in channels A & B is probably much shorter than 3s (which is too long delay value), saying some microseconds or so. But when duration of this mismatch exceed 3s, system would be lockouted. |
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